Digital controller for a voltage regulator module

ABSTRACT

A digital controller for a voltage regulator module (VRM) having single phase or multiphase power converters, and an optional dynamic conversion circuit, is disclosed. The digital controller improves the transient response of the VRM during harsh load current transients, and permits a substantial reduction in output capacitance of the VRM. When used with multiphase interleaved power converters, for a given load current requirement, the digital converter permits the number of interleaved phases of the VRM to be minimized. A VRM with the digital controller demonstrates low cost, high power density, high efficiency, and fast transient response.

FIELD OF THE INVENTION

The invention generally relates to a voltage regulator module (VRM), andparticularly to control methods and devices for enhancing the transientresponse of a VRM under dynamic load conditions.

BACKGROUND OF THE INVENTION

A voltage regulator module (VRM) is used to regulate a DC voltagesupplied to a load, such as microprocessor. A VRM includes a powerconverter, such as a DC-DC converter, and may include other componentssuch as a controller for controlling operation of the power converter.An example of a DC-DC converter is a synchronous buck converter, asshown in FIG. 1, which has minimal components, and therefore is widelyused in VRM applications. In microprocessor applications, the inputvoltage to the VRM is typically 12 V_(DC). The output voltage may be 5.0V_(DC), 3.3 V_(DC), or lower.

As microprocessors become more advanced, required supply voltages becomelower. Supply voltages are expected to be as low as 0.5 V_(DC) in thenear future, which will require currents up to 200 A or more. Currently,the CPU of a typical personal computer operates at 3 GHz, and operatingfrequencies are expected to reach 10 GHz in the near future. Aconsequence of the low supply voltage and high clock frequency is thehigh slew rate (di/dt) of the load current at power up. For example,when a microprocessor wakes from sleep mode to full operating mode, thestep of the output current may be as high as 200 A, with a slew rate of1,000 A/μs or higher. The slew rate may be over 1,000 A/μs in futuredesigns. The voltage supplied to current microprocessors is required tobe regulated within 2%, and 1% for future VRMs (“VRM 9.1 DC-DC converterdesign guidelines”, Intel Order Number 298646-001, January 2002). Theabsolute value of such voltage regulation is currently 30 mV and 10 mVfor future designs. Such tight voltage regulation is required tomaintain normal operation of CMOS transistors in the microprocessorunder all conditions. For instance, under worst case (high slew rate ofthe output current) conditions, the output voltage should not drop bymore than 30 mV to avoid abnormal operation of the CPU. However, thevoltage drop of VRMs based on existing designs may be so large that theoutput voltage regulation limit may easily be exceeded.

Various VRM topologies and control methods have been proposed in anattempt to satisfy the transient response requirements ofmicroprocessors. However, such designs are not well-suited to theharsher dynamic requirements of next generation microprocessors.

For example, simply increasing the output capacitance can reduce theoutput voltage ripple, and also help maintain the output voltage duringa sudden load change. However, for a single phase 1.5 V_(DC)/25 A VRM,for instance, a design that can meet the steady sate and transientvoltage regulation specification typically requires at least 5,000 μFoutput capacitance. Such filter capacitors are bulky and expensive. Itis estimated that for a VRM supplying 0.5 V_(DC) at 100 A, the requiredoutput capacitance would be more than 10,000 μF, and should haveconsiderably lower equivalent series inductance (ESL) and equivalentseries resistance (ESR) to be effective during load transients. FIG. 2(top curve only) shows such a relationship between the outputcapacitance and load current for typical prior VRMs. Although multiphasetopology, which helps to reduce output capacitance, may be used forapplications when the load current exceeds 20 A, the value of thecapacitance is still exceedingly high at high load current.

Reducing the output inductance of a buck converter can improve itsdynamic response. However, the inductance can not be reduced unbounded,otherwise the output voltage ripple will increase above acceptablelimits (e.g., above 10 mV for next generation microprocessors). Theincreased voltage ripple will in turn reduce the room for the outputvoltage drop during load dynamics. In addition, a larger ripple currentthrough the filter inductor implies a larger RMS current through thepower switches, which will reduce the overall efficiency of the VRMunder steady state operation. Moreover, even though the inductance canbe reduced for a faster dynamic response, it is not enough to provideadequate response speed for future microprocessors if the outputcapacitance is required to be small to reduce cost and to satisfy sizeand volume constraints.

Multiphase interleaved VRM topology provides two or more powerconverters in parallel and shares the same output capacitors amongconverters. In each of the power converters (or each phase), the filterinductor can be smaller than that of a single phase VRM to achieve afaster dynamic response. The large output voltage ripple in each phasedue to the small inductance can be cancelled by the ripple of otherphases. The more phases are in parallel, the smaller the ripple will be,but at the expense of increased circuit cost. Multiphase topology cantherefore enhance the output current capability of a VRM. However, ifthe output current can be provided by a single phase VRM or a VRM withfewer phases, then adopting a multiphase topology or adding extra phasesin parallel solely for the purpose of reducing the ripple voltage addsconsiderable complexity, size, and cost. More importantly, it is verydifficult for a conventionally-controlled multiphase VRM to achieve thedynamic response required by future microprocessors, without having verylarge output capacitance.

Current mode control has a faster dynamic response than that ofconventional voltage mode control in situations where only a smallperturbation such as a small load change occurs. However, its dynamicperformance is not superior to that of voltage mode control when a largetransient occurs. More importantly, in current mode control, the currentis detected by employing a sensing resistor or a current transformer.However, for an output current of 100 A or higher, it would beimpractical to use a resistor to accurately and efficiently sense thecurrent. On the other hand, a current transformer is bulky and thesensed current must be averaged, resulting in further increases in thereaction time and drop in the output voltage when a large load stephappens.

The voltage droop control method takes advantage of the upper and lowerlimits of the VRM output voltage to gain more room for dynamicresponses. When the load current is low, the reference voltage is set tobe higher than the nominal value but still within the specified upperlimit. When a load step-up happens, the output voltage will drop butwill have more room to drop than if it were starting from the nominalvalue. When the load current is high, the reference voltage is set to below; thus when a load step-down happens, the output voltage has moreroom for the overshoot. However, this small room is far from beingenough to handle the harsh dynamic requirements of next generationmicroprocessors. Moreover, the voltage droop control method alsorequires current sensing, which again is not very practical, asdiscussed above.

Operating the power converter at a very high frequency will improve thedynamic response of a VRM having a very small output capacitance.However, design of an efficient power converter operating at a very highfrequency is difficult. Further, the efficiency of a power converterdecreases eventually to an unacceptable or unsatisfactory level as itsoperating frequency increases. In general, increasing the switchingfrequency of a power converter solely for the purpose of improving thedynamic performance is not an optimum solution.

A stepping inductor method for fast transient response of switchingconverters is disclosed in U.S. Pat. No. 6,188,209, issued Feb. 13, 2001to Poon et al. Relative to the basic buck converter, this designrequires significantly more circuit components, which may be difficultand expensive to implement in a multiphase interleaved VRM, because allof the components need to be repeated for each phase. Moreover, thecontrol circuit for load transients is analog based and the outputvoltage is compared to fixed hysteresis reference voltages to triggerand terminate the transient operation of the converter independently ofthe load current conditions. This implies that the transient circuitworks the same way for a 25%, 50%, and 100% load step, for instance.Therefore, the voltage response during a load transient is not regulatedand may exceed the specified limits of the output voltage during manyload conditions.

A transient override circuit is proposed in U.S. Pat. No. 6,696,882,issued Feb. 24, 2004 to Markowski et al. This circuit detects the loadvoltage level to trigger a transient operation mode of the VRM. Intransient operation mode, the power switch of a buck converter is forcedto be turned on, and the synchronous power switch of the buck converteris turned off, to override the current through the output inductor.However, the circuit and control method are analog based, and,importantly, are not able to regulate the output voltage during thetransient.

Peterchev et al. (“Architecture and IC implementation of a digital VRMcontroller”, IEEE Transactions on Power Electronics, 18 (1):356-364,2003) relates to a digital controller for a dc-dc switch mode converter.However, the reference focuses on digital control only for normal steadystate operation. Saggini et al. (“An innovative digital controlarchitecture for low-voltage, high current dc-dc converters with tightvoltage regulation”, IEEE Transactions on Power Electronics, 19(1):210-218, 2004) addresses digital control for improving the transientresponse of a VRM. However, this reference teaches a variable frequencycontrol method in combination with voltage droop control, which requiresaccurate sensing of the load current. U.S. patent Publication No.2004/015098, published Aug. 5, 2004, relates to a digital controller fora VRM; however, some of the operations carried out by this controllerare effected through analog circuitry.

SUMMARY OF THE INVENTION

According to one aspect of the invention there is provided a digitalcontroller for a switching DC-DC converter of a voltage regulatormodule, comprising: a voltage sensor for sensing an output voltage ofthe DC-DC converter and generating a corresponding digital signal; meansfor determining an expected output current of the DC-DC converter fromthe digital signal; and means for generating at least one gate signalwhen: (i) the expected output current is greater than an operatingcurrent; and/or (ii) the sensed output voltage is less than a thresholdoutput voltage; wherein the at least one gate signal is provided to atleast one switch of the DC-DC converter, the at least one gate signalturning on a first switch that increases current output of the DC-DCconverter and/or turning off a second switch that limits output currentof the DC-DC converter.

In one embodiment, the means for generating at least one gate signal maygenerate a gate signal for each switch in the DC-DC converter.

The DC-DC converter may be of an isolated or a non-isolated topology,such as boost, buck, or buck-boost. In a preferred embodiment, the DC-DCconverter is a buck converter.

In one embodiment, the voltage regulator module may include a dynamicconversion circuit, and the means for generating at least one gatesignal generates a gate signal for at least one switch in the dynamicconversion circuit. In another embodiment the means for generating atleast one gate signal may generate a gate signal for each switch in thedynamic conversion circuit and for at least one switch in the DC-DCconverter.

The at least one gate signal may be a pulse train of higher frequencythan a switching frequency of the DC-DC converter. The at least one gatesignal may be pulse width modulated.

In a further embodiment, two or more switching DC-DC converter circuitsmay be included in the voltage regulator module, wherein the means forgenerating at least one gate signal comprises means for generating agate signal for at least one switch of each DC-DC converter. The voltageregulator module may include a dynamic conversion circuit, and the meansfor generating at least one gate signal may comprise means forgenerating a gate signal for each switch in the dynamic conversioncircuit and for at least one switch of each DC-DC converter. The two ormore DC-DC converters may be of an isolated or a non-isolated circuittopology. Preferably, at least one DC-DC converter is a buck converter.

According to another aspect of the invention there is provided a methodfor digitally controlling a voltage regulator module including aswitching DC-DC converter, comprising: sensing an output voltage of theDC-DC converter and generating a corresponding digital signal;determining an expected output current of the DC-DC converter from thedigital signal; generating at least one gate signal when: (i) theexpected output current is greater than an operating current; and/or(ii) the sensed output voltage is less than a threshold output voltage;and providing the at least one gate signal to at least one switch of theDC-DC converter of the voltage regulator module; wherein the at leastone gate signal turns on a first switch that increases current output ofthe DC-DC converter and/or turns off a second switch that limits outputcurrent of the DC-DC converter.

In one embodiment, the method may further comprise generating a gatesignal for each switch in the DC-DC converter.

In one embodiment, the voltage regulator module may include a dynamicconversion circuit, the method further comprising generating a gatesignal for a switch of the dynamic conversion circuit. In anotherembodiment the method may further comprise generating a gate signal fora switch in the dynamic conversion circuit and for at least one switchof the DC-DC converter.

In accordance with the method, the DC-DC converter may be of an isolatedor a non-isolated topology, such as buck, boost, or buck-boost. In apreferred embodiment, the DC-DC converter is a buck converter.

In one embodiment, the method may further comprise generating the gatesignal as a pulse train of higher frequency than a switching frequencyof the DC-DC converter. The method may further comprise pulse widthmodulating the gate signal.

In another embodiment, the voltage regulator module may include two ormore DC-DC converters, the method further comprising generating at leastone gate signal for at least one switch of each DC-DC converter. Themethod may further comprise generating a gate signal for each switch ineach DC-DC converter. The voltage regulator module may include a dynamicconversion circuit, and may further comprise generating a gate signalfor a switch in the dynamic conversion circuit. The method may furthercomprise generating a gate signal for at least one switch in each DC-DCconverter and for a switch in the dynamic conversion circuit. Each DC-DCconverter may be of an isolated or a non-isolated circuit topology, suchas buck, boost, or buck-boost. Preferably, at least one DC-DC converteris a buck converter.

In some embodiments of the method, determining an expected outputcurrent of the DC-DC converter from the digital signal may comprisecalculating the output current from a linear or a non-linear function.In other embodiments, determining an expected output current of theDC-DC converter from the digital signal may comprise determining acorresponding current value from a look-up table.

According to another aspect of the invention there is provided a voltageregulator module comprising at least one DC-DC power converter circuitand a digital controller as described herein. The voltage regulatormodule may further comprise a dynamic conversion circuit as describedherein.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described, by way of example, with referenceto the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a prior art single phase synchronousbuck converter;

FIG. 2 is a plot of estimated output capacitance versus load current forthe invention compared with prior art VRMs;

FIG. 3 is a schematic diagram of a single phase VRM circuit including adigital controller according to an embodiment of the invention;

FIG. 4 is a block diagram of a digital controller for a single phase VRMaccording to the invention;

FIG. 5 is a plot of single phase VRM waveforms during the steady stateand during a transient state according to the control method of theinvention;

FIG. 6 is a flow chart of the control algorithm of an embodiment of adigital controller according to the invention;

FIG. 7 is a schematic diagram of a multiphase interleaved VRM with adynamic conversion circuit and a digital controller according to theinvention;

FIG. 8 is a block diagram a digital controller for a multiphase VRMembodiment;

FIG. 9 is a plot of multiphase VRM waveforms during steady state andduring a transient state according to the control method of theinvention;

FIG. 10 is a plot of the load current change αI_(o) as a function of theoutput voltage slew rate dv/dt; and

FIG. 11 is a plot showing the results of a simulation comparing theoutput voltage waveforms of a VRM of the invention and a conventionalvoltage mode controlled VRM during a load transient, in which V_(g)=12V_(DC), V_(o)=1.5 V, I_(o)=25 A, C_(o)=500 μF, f_(s)=250 kHz, and theload steps from 0.5 A to 25 A.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Digital control has many advantages over analog control in a powerconverter. One of the most important advantages relates to theflexibility of digital control. Various control schemes that may bedifficult to implement in analog control become feasible when digitalcontrol is applied. However, no previous digital controllers for VRMsprovide satisfactory solutions for transient load conditions,particularly the transients expected to be presented by futuremicroprocessors.

A digital controller as described herein provides a novel solution tothe control of a VRM during transients, by employing voltage sensing ofthe VRM output voltage. By sensing minute changes in the output voltage,and relating the output voltage to the corresponding required outputcurrent (e.g., predicting the output current from the sensed outputvoltage), a digital controller as described herein may respond quicklyto sudden demands for current that would otherwise result in asubstantial drop in output voltage, compromising performance of theload. As exemplified by the embodiments described herein, the digitalcontroller of the invention has been optimized to work in conjunctionwith either a dynamic conversion circuit and a power converter, such asa buck converter, or with only a power converter, as use of the digitalcontroller to enhance performance of any power converter may beaccomplished with only minor modifications to the embodiments describedherein.

By implementing the digital controller and the control method of theinvention, increasing the switching frequency of the DC-DC converter isunnecessary, because an increased switching frequency does not furtherimprove the dynamic response of the converter. The switching frequencymay be kept below 500 kHz to achieve a higher efficiency and at the sametime maintain a very fast dynamic response with greatly reduced outputcapacitance. The greatly reduced output capacitance enables the use ofceramic capacitors, which are smaller in size and have a much smallerequivalent series resistance (ESR). Consequently, a VRM according to theinvention will require less space on a PCB and cost will be reduced.Further, the digital implementation offers great flexibility, includingexternal programming, such that no analog components need to besubstituted under different conditions. Factors such as tolerance,temperature, and aging of components have no effect on components suchas the compensator due to the digital implementation.

According to one aspect of the invention there is provided a voltageregulator module, comprising a power conversion circuit, an optionaldynamic conversion circuit, and a digital controller. The load may be ofvarious devices that require tight output voltage regulation. Amicroprocessor is an example of such a load due to its large currentconsumption and the extreme load transients it presents to the VRM. Forthese reasons, a microprocessor will be considered as the load for theVRM in this disclosure. The power conversion circuit of the VRM is powerconverter, typically a DC-DC voltage converter such as a synchronousbuck converter, but is not limited thereto. Other isolated andnon-isolated power converter circuits, such as, for example, boost andbuck-boost, may also be used. The power converter may be single phase ormultiphase interleaved to regulate the output voltage, depending on howmuch load current is needed.

The dynamic conversion circuit is a circuit capable of respondingrapidly to sudden changes in the load connected to the VRM output. Asudden change in the load, such as an increase in current consumption,results in a decrease in the output voltage from its nominal value. Sucha load transient represents a deviation in output current of the powerconverter from its operating current (i.e., steady-state current). Thedynamic conversion circuit responds to such transient decreases inoutput voltage by transiently increasing the output current of the DC-DCconverter, thereby preventing further decreases in output voltage. Thus,the dynamic conversion circuit substantially improves the voltageregulation of the VRM under dynamic load conditions. An example of asuitable dynamic conversion circuit is set forth in our co-pending U.S.patent application Ser. No. ______, incorporated herein by reference inits entirety. Such a dynamic conversion circuit may be used with anyisolated or non-isolated switching DC-DC converter, such as, forexample, buck, boost, or buck-boost, single phase or multiphaseinterleaved, for any load requiring tight voltage regulation under bothsteady-state and transient conditions.

In the embodiment shown in FIG. 3, a VRM comprises a buck converter 10,an optional dynamic conversion circuit 20, and a digital controller 30,and the VRM is connected to a dynamic load 100 (e.g., a microprocessor).The power converter 10 includes switching power devices S₁ and S₂, andan output filter inductor L_(o) and capacitor C_(o). The dynamicconversion circuit 20 includes an auxiliary power switch S_(aux) inseries with an auxiliary inductor L_(aux). The dynamic conversioncircuit is connected in parallel with the power converter 10. In analternative embodiment the dynamic conversion circuit 20 may beconnected in parallel with only the output inductor L_(o) of the powerconverter 10. In either case, the same configuration of digitalcontroller 30 may be used. Further, other configurations of a dynamicconversion circuit may also be used. In various embodiments, the digitalcontroller 30 may be used to control the gate signal of the powerswitches S₁ and/or S₂, and/or the auxiliary switch S_(aux) duringtransients.

A block diagram of an embodiment of the digital controller 30 is shownin FIG. 4. This embodiment is for a single phase VRM having a singlepower converter, for example a buck converter, and an optional dynamicconversion circuit. The digital controller includes six major functionblocks:

1) An analog-to-digital converter (ADC) 40 which senses the outputvoltage at the load and converts the analog voltage signal intodigitized bits. The speed and resolution (e.g., number of bits) of theADC may be specified according to the required performance and thedesign considerations. For example, we have found that a 12-bit, 125MSPS (mega samples per second), ADC, part number AD9433-125, availablefrom Analog Devices, is suitable.

2) A digital signal processing (DSP) block 50, which receives the outputfrom the ADC 40 and processes the sampled output voltage based on analgorithm, an example of which is discussed below with respect to FIG.6;

3) A digital pulse width modulation (PWM) block 60, which receivesoutput from the DSP block 50 and generates a digitized PWM gate signalsfor the switches of the power converter, and optionally for an auxiliarycircuit if used;

4) A gate of power converter block 70, which generates the synchronousgate signals for the two switches of the power converter;

5) An optional gate of dynamic converter block 80, which generates thegate signal for the switch S_(aux) of the optional dynamic conversioncircuit; and

6) A gate drive block 90, which drives the gates of the switches of thepower converter and optional dynamic conversion circuit with thesynchronized PWM signals.

Preferably the digital controller is implemented as an integratedcircuit. However, the ADC and the gate drive block may not benecessarily integrated into the digital controller device; that is,either one or both of these blocks may be physically discrete from suchan integrated digital controller device.

Operation of the digital controller will now be described with referenceto FIGS. 4 and 5. In normal steady state operation of the powerconverter or when the load transient is within certain range, the pulsewidth of the gate signal is determined by the sensed load voltage, thenature of the power converter, and the way the system is compensated.The sampled load voltage is compared with a reference voltage in the DSPblock 50 shown in FIG. 4. The discrete error signal is compensated bythe compensator 52, which may be a digitally-implemented compensatorsuch as, for example, a proportional integral derivative (PID), PI, TypeII, Type III, or proportional/differential (PD) lead compensator. Thecompensator is selected according to the power converter requirements,based on voltage mode control. The synchronous gate signals of one phaseof the converter during steady state are shown in FIG. 5 at time t₀-t₂and t₃-∞, Normal Steady State Mode. The frequency of the gate signal isalways fixed. The pulse width or duty cycle of the gate signal is alsostabilized during steady state operation. At time t₁ in FIG. 5, a loadtransient occurs. After a delay of t_(d), at time t₂, the converterenters Dynamic Mode. The delay t_(d) is due to the sampling andprocessing time of the digital controller. Once a load transient occurs,the duty cycle of the synchronous gate signal is adjusted, determined byhow the system is compensated, and relates to factors such as thecrossover frequency and the gain of the compensator. However, withoutthe digital controller of the invention, the change in the duty cycle ofthe gate signal is not sufficient to handle a dramatic load change.Under such circumstances the occurrence of the next gate pulse islimited by the switching frequency of the power converter, and does notoccur fast enough to transfer power to the output and minimize theoutput voltage drop during a load transient.

In the DSP block 50 in FIG. 4, the sampled load voltage is sent to adigital filter 54 to filter out noise and then is processed at 56 toobtain the derivative of the output voltage. The derivative of theoutput voltage is sent to the PWM function 57 for further processing.The algorithm for dynamic function block 58 determines when the dynamicmode will be triggered and terminated. The steady state PWM gating andthe dynamic gating generated in the digital PWM block 60 are combined toform the gate signal for one phase, which will then be shifted formultiphase switching power devices. This combined signal is thus forsteady state operation and dynamic operation when a transient happens.

The dynamic gate pattern is generated according to the process given inthe flow chart shown in FIG. 6, where reference numerals correspondingto those in FIG. 4 indicate like steps. In the flow chart, the sampledvoltage is filtered by a digital filter 54 to remove noise, and then isprocessed at 56 to obtain the derivative of the sampled voltage.

In one embodiment, the algorithm for dynamics 58 uses the derivative ofthe sampled voltage to calculate, at 58 a, the change in load currentΔL_(o) according to a linear or non-linear function (e.g., algebraic,trigonometric, exponential) (see equation (1)). The function is based oncharacteristics such as the output inductance, capacitance, equivalentseries resistance (ESR), switching frequency, input/output voltage, andthe parameters of the compensator. For example, the voltage vs. currentrelationship derived from equation (1) when ƒ is a linear function isplotted in FIG. 10. This plot shows that once the derivative of theoutput voltage is obtained, the load step can be predicted.ΔI _(o)=ƒ(dV _(o) /dt)  (1)

In another embodiment, rather than calculate the change in outputcurrent, the algorithm for dynamics stores data relating to possibleoutput currents for various output voltages, and looks up theappropriate output current for any given sensed voltage. The advantagesof such a look-up table approach are improved speed and the ability toimplement functions which might be difficult to model mathematically(e.g., using curve-fitting approximations).

Once the derivative of the output voltage exceeds a certain value,indicating that the load current step will exceed a certain thresholdvalue, the algorithm for dynamics 58 (FIGS. 4 and 6) will initiate apulse for dynamic. Specifically, at steps 58 b and 58 c of FIG. 6, ifthe load current increase exceeds a threshold value, and/or the voltagedrop exceeds a threshold value, the dynamic gate pulse will be started.However, if both the output voltage drop and the load current step donot exceed their given threshold values, the dynamic gate pulse will notbe initiated, in which case the combined gate signal is the gate signalfrom the path of the steady state PWM for the main switch in the flowchart of FIG. 6.

The dynamic gate pulse remains high for a certain period of time.Theoretically, when the current through the output inductor L_(o)reaches the value that the output current should step to (e.g.,according to equation (1)), the dynamic gate pulse should be turned off.However, in accordance with the invention it is not necessary to measurethe current through the inductor to determine when to turn off thedynamic gate pulse. Rather, it is only necessary to turn of the dynamicgate pulse after a period of time t_(a) equal to that required for theoutput current to rise to the predicted value (e.g., according toequation (1)). The time t_(a) is calculated by the algorithm fordynamics 58 of the DSP block 50 of the digital controller. The timet_(a) is a function of one or more parameters of the power convertersuch as, for example, the output inductance, capacitance, equivalentseries resistance (ESR) of the output capacitor, switching frequency,input/output voltage, and parameters of the compensator, and a functionof the load current step. Equation (2) reveals the relationships toobtain the time t_(a). $\begin{matrix}{t_{\alpha} = {\frac{\Delta\quad{I_{o} \cdot L_{o}}}{V_{g} - V_{o}} = \frac{{f( {{\mathbb{d}V_{o}}/{\mathbb{d}t}} )} \cdot L_{o}}{V_{g} - V_{o}}}} & (2)\end{matrix}$

As shown in FIGS. 4 and 6, the dynamic gate pulse of duration t_(a),determined at 58 e, is combined at 64 with the steady state PWM to formthe gate signal of the power converter switch for both steady state andtransient situations. The combination process is similar to an OR logicfunction. The waveform of the combined gate signals generated at 92 isshown in the flow chart in FIG. 6 and in FIG. 5. Thus, during thedynamic mode, once a load transient is detected, the switch S₁ in FIG. 3will be turned on and kept on for a period of time t_(a), calculated bythe digital controller, while the switch S₂ will be kept off during thisperiod of time. Thus, with the digital controller, the gate pulse startsin time, and the pulse width is not limited by the bandwidth of theclosed control loop and is wide enough to supply the current from theinput to the output through the filter inductor L_(o) to help maintainthe output voltage during the transient.

The optional dynamic conversion circuit may also be activated by thedigital controller during the load transient. When switch S₁ is turnedon and switch S₂ is turned off for a time period of t_(a), the switchS_(aux) of the dynamic conversion circuit is turned on and off by thegate signal generated at 94. It is noted that the inductor L_(aux) inthe dynamic conversion circuit has a substantially smaller value thanthat of L_(o), such that the power transferred from the input to theoutput of the VRM is further accelerated. Moreover, turning S_(aux) ofthe dynamic conversion on and off may comprise modulating (e.g., PWM)the gate of S_(aux) during a load transient. A PWM modulation block forthe auxiliary switch is shown in FIGS. 4 and 6, and may provide asuitable pattern of gate switching such as, for example, those shown inFIG. 5 and described below.

The first gate pattern of S_(aux) (option 1 in FIG. 5) switches S_(aux)at a fixed switching frequency much higher than that of the main powerconverter circuit. For example, the switching frequency of S_(aux) maybe 2 to 10 times, 2 to 100 times, or higher, than the switchingfrequency of the power converter, as may be possible to achieve withavailable technology. The pulse width of the gate signal is modulated asa constant, predetermined by the digital controller.

The second gate pattern of S_(aux) (option 2 in FIG. 5) also switchesS_(aux) at a fixed frequency much higher than that of the main powerconverter circuit. The gate signal is pulse width modulated based onvoltage mode control. The output voltage of the VRM is sensed andcompared with the reference voltage. The error between the sensed outputvoltage and the reference voltage is compensated by a compensatorsimilar to the compensator of the main power circuit, but with a largergain. The pulse width of the gate is varied according to how the loop iscompensated. For example, the loop may be compensated by a Type IIIcompensator with a high gain.

The third gate pattern of S_(aux) (option 3 in FIG. 5) also switchesS_(aux) at a fixed frequency much higher than that of the main powercircuit. The pulse width of the gate signal is predefined to be largeinitially and then decreases linearly as a function of time. Thedecreasing rate of the duty cycle is also predefined or calculated bythe digital controller.

The PWM modulated signal for the auxiliary switch S_(aux) is combinedwith the dynamic gate pulse at 68 to form the gate signal for S_(aux).The combination process is similar to an AND logic function, as shown inFIGS. 4 and 6.

In a second embodiment, shown in FIG. 7, the invention relates to amultiphase interleaved VRM with a dynamic conversion circuit and adigital controller. FIG. 7 shows a multiphase interleaved VRM with fourpower converter phases, although more or fewer phases are possible,depending on the amount of output current required. Shown in theembodiment of FIG. 7 are the main components of the interleaved VRM: thefour power converter phases 210, the dynamic conversion circuit 220, andthe digital controller 230. In this example, the load 300 is amicroprocessor. The switches S_(a1), S_(b1) and the inductor L_(o1) formthe first phase of the multiphase interleaved power converter, eachparallel phase being a synchronous buck converter. Other powerconverters, such as boost, buck-boost, isolated, and non-isolated couldalso be used. All four phases share the same output capacitor CO. Theauxiliary power switch S_(aux) and inductor L_(aux) form the optionaldynamic converter of the VRM, which is connected in parallel with thefour parallel power converters.

The digital controller 230 for the interleaved VRM is shown in the blockdiagram of FIG. 8. The digital controller 230 has the same componentsand functions in the same way as the digital controller 30 in the singlephase VRM described above (FIG. 4), except that the gate signalgeneration portion is now a multiphase gate generator 270, whichgenerates the gate signals for paralleled buck converters. Themultiphase gate generator block 270 includes a phase shift generator 272for receiving the gate signal from the digital PWM, and four synchronousgating circuits 274 to 277, one for each of the four phases. Eachsynchronous gating circuit output is fed to a corresponding gate drivecircuit in the gate drive block 290. The gate drive block 290 drives andsends the phase-shifted PWM gate signals to the power switches of eachparalleled branch of the power converter. Optionally, it also drives andsends the gate signal to the auxiliary switch of the dynamic conversioncircuit. Operation of the digital controller is substantially the sameas for the single phase embodiment (see FIG. 6), in that the steadystate PWM gating and the dynamic gating generated in the digital PWMblock 260 are combined to form the gate signal for one phase. However,in the multiphase embodiment, this gate signal is then phase shifted bythe phase shift generator 272 for multiphase switching power converters.Also, as in the single phase embodiment, the period t_(a) at which toturn off the dynamic gate pulse may be calculated by the DSP block 250of the digital controller. The time t_(a) is a function of buckconverter parameters such as output inductance, output capacitance, ESRof the output capacitor, switching frequency, input/output voltage,parameters of the compensator, as well as the load current step.Equation (3) describes the relationship to obtain the time t_(a).$\begin{matrix}{t_{\alpha} = {\frac{\Delta\quad{I_{o} \cdot L_{o}}}{4 \cdot ( {V_{g} - V_{o}} )} = \frac{{f( {{\mathbb{d}V_{o}}/{\mathbb{d}t}} )} \cdot L_{o}}{4 \cdot ( {V_{g} - V_{o}} )}}} & (3)\end{matrix}$

The synchronous gate signals of one phase of the converter during steadystate are shown in the period referred to as Normal Steady State Mode(t₀-t₂ and t₃∞) in FIG. 9. The frequency of the gate signal is alwaysfixed. The pulse width or duty cycle of the gate signal is alsostabilized during steady state operation. At time t₁ in FIG. 9, a stepload occurs. After a delay of t_(d), at time t₂, the converter entersDynamic Mode. The delay t_(d) is due to the sampling and processing timeof the digital controller. Once a load transient occurs, the incrementof the duty cycle of the synchronous gate signal is determined by howthe system is compensated, and relates to factors such as the crossoverfrequency and the gain of the compensator.

During Dynamic Mode, the switches S_(a1), S_(a2), S_(a3), and S_(a4) areturned on and kept on for a duration of time t_(a), as calculated by thedigital controller, while the switches S_(b1), S_(b2), S_(b3), andS_(b4) are kept off during this period of time. Thus the gate pulsestarts in time and the pulse width will not be limited by the bandwidthof the closed control loop and will be wide enough to supply the currentfrom the input to the output through the filter inductors L_(o1),L_(o2), L_(o3), and L_(o4) to help maintain the output voltage duringthe transient.

The optional dynamic conversion circuit is also activated by the digitalcontroller during the load transient. When switches S_(a1), S_(a2),S_(a3), and S_(a4) are turned on and switches S_(b1), S_(b2), S_(b3),and S_(b4) are turned off for a time period Of t_(a), the switch S_(aux)of the dynamic conversion circuit is turned on and off. In variousembodiments the switch S_(aux) may be modulated according to a desiredgate signal drive pattern, three examples of which are shown in FIG. 9as options 1 to 3. Options 1 to 3 are the same as those shown in FIG. 5and described above with respect to the single phase VRM embodiment.

The invention is further illustrated by way of the followingnon-limiting example.

EXAMPLE

A voltage regulator module based on a buck converter and including adigital controller as described above and a dynamic conversion circuitwas simulated in PSPICE v. 9.0 and its performance evaluated withrespect to a VRM based on a typical buck converter. The input and outputvoltages of the two VRMs was 12 V_(dc) and 1.5 V_(dc) respectively, andthe switching frequency of the two circuits was 250 kHz. The ratedoutput current was 25 A and the load transient was from 0.5 A to 25 A,at a slew rate of 1000 A/μs. The results of the simulation are shown inFIG. 11, where it can be seen that the voltage drop of the VRM of theinvention was less than 10% of that of the typical VRM. According to thesimulation, to avoid exceeding a 70 mV output voltage drop at a 100%load current transient (25 A), an output capacitance of only 500 μF wasrequired. In contrast, the conventional voltage mode controlled singlephase VRM needed at least 5000 μF output filter capacitance. This is anapproximately 6-fold reduction in output capacitance, which representssubstantial savings in space on the printed circuit board, andultimately in cost.

All cited documents are incorporated herein by reference in theirentirety.

It will be understood by those skilled in the art that this descriptionis made with reference to preferred embodiments and that it is possibleto make other embodiments employing the principles of the inventionwhich fall within its spirit and scope as defined by the appendedclaims.

1. A digital controller for a switching DC-DC converter of a voltageregulator module, comprising: a voltage sensor for sensing an outputvoltage of the DC-DC converter and generating a corresponding digitalsignal; means for determining an expected output current of the DC-DCconverter from the digital signal; and means for generating at least onegate signal when: (i) the expected output current is greater than anoperating current; and/or (ii) the sensed output voltage is less than athreshold output voltage; wherein the at least one gate signal isprovided to at least one switch of the DC-DC converter, the at least onegate signal turning on a first switch that increases current output ofthe DC-DC converter and/or turning off a second switch that limitsoutput current of the DC-DC converter.
 2. The digital controller ofclaim 1, wherein the means for generating at least one gate signalgenerates a gate signal for each switch in the DC-DC converter.
 3. Thedigital controller of claim 1, wherein the DC-DC converter is of anisolated or a non-isolated topology.
 4. The digital controller of claim1, wherein the DC-DC converter is a buck converter.
 5. The digitalcontroller of claim 1, wherein the voltage regulator module includes adynamic conversion circuit, and the means for generating at least onegate signal generates a gate signal for at least one switch in thedynamic conversion circuit.
 6. The digital controller of claim 5,wherein the means for generating at least one gate signal generates agate signal for each switch in the dynamic conversion circuit and for atleast one switch in the DC-DC converter.
 7. The digital controller ofclaim 1, wherein the at least one gate signal is a pulse train of higherfrequency than a switching frequency of the DC-DC converter.
 8. Thedigital controller of claim 1, wherein the at least one gate signal ispulse width modulated.
 9. The digital controller of claim 1, wherein twoor more switching DC-DC converter circuits are included in the voltageregulator module, wherein the means for generating at least one gatesignal comprises means for generating a gate signal for at least oneswitch of each DC-DC converter.
 10. The digital controller of claim 9,wherein the voltage regulator module includes a dynamic conversioncircuit, and the means for generating at least one gate signal comprisesmeans for generating a gate signal for each switch in the dynamicconversion circuit and for at least one switch of each DC-DC converter.11. The digital controller of claim of claim 9, wherein the two or moreDC-DC converters are of an isolated or a non-isolated circuit topology.12. The digital controller of claim of claim 9, wherein at least oneDC-DC converter is a buck converter.
 13. A method for digitallycontrolling a voltage regulator module including a switching DC-DCconverter, comprising: sensing an output voltage of the DC-DC converterand generating a corresponding digital signal; determining an expectedoutput current of the DC-DC converter from the digital signal;generating at least one gate signal when: (i) the expected outputcurrent is greater than an operating current; and/or (ii) the sensedoutput voltage is less than a threshold output voltage; and providingthe at least one gate signal to at least one switch of the DC-DCconverter of the voltage regulator module; wherein the at least one gatesignal turns on a first switch that increases current output of theDC-DC converter and/or turns off a second switch that limits outputcurrent of the DC-DC converter.
 14. The method of claim 13, furthercomprising generating a gate signal for each switch in the DC-DCconverter.
 15. The method of claim 13, wherein the voltage regulatormodule includes a dynamic conversion circuit, further comprisinggenerating a gate signal for a switch of the dynamic conversion circuit.16. The method of claim 15, further comprising generating a gate signalfor a switch in the dynamic conversion circuit and for at least oneswitch of the DC-DC converter.
 17. The method of claim 13, wherein theDC-DC converter is of an isolated or a non-isolated topology.
 18. Themethod of claim 13, wherein the DC-DC converter is a buck converter. 19.The method of claim 13, further comprising generating the gate signal asa pulse train of higher frequency than a switching frequency of theDC-DC converter.
 20. The method of claim 13, further comprising pulsewidth modulating the gate signal.
 21. The method of claim 13, whereinthe voltage regulator module includes two or more DC-DC converters,further comprising: generating at least one gate signal for at least oneswitch of each DC-DC converter.
 22. The method of claim 21, furthercomprising generating a gate signal for each switch in each DC-DCconverter.
 23. The method of claim 21, wherein the voltage regulatormodule includes a dynamic conversion circuit, further comprisinggenerating a gate signal for a switch in the dynamic conversion circuit.24. The method of claim 23, further comprising generating a gate signalfor at least one switch in each DC-DC converter and for a switch in thedynamic conversion circuit.
 25. The method of claim 21, wherein eachDC-DC converter is of an isolated or a non-isolated circuit topology.26. The method of claim 21, wherein at least one DC-DC converter is abuck converter.
 27. The method of claim 13, wherein determining anexpected output current of the DC-DC converter from the digital signalcomprises calculating the output current from a linear or a non-linearfunction.
 28. The method of claim 13, wherein determining an expectedoutput current of the DC-DC converter from the digital signal comprisesdetermining a corresponding current value from a look-up table.
 29. Avoltage regulator module comprising at least one DC-DC power convertercircuit and the digital controller of claim
 1. 30. The voltage regulatormodule of claim 29, further comprising a dynamic conversion circuit.